1. Technical Field
The embodiments described herein relate to semiconductor integrated circuits, and more particularly, to apparatus and methods for performing stable duty cycle correction operation on clocks in a semiconductor integrated circuit.
2. Related Art
In general, semiconductor integrated circuits, such as synchronous dynamic random access memories (SDRAMs), process data using clocks to improve the operational speed of the circuit. Accordingly, if a ratio between a rising edge period and a falling edge period, i.e., the duty ratio, of clocks related or used for processing data is mismatched, the operation efficiency can be decreased. However, a clock that is actually used in a semiconductor integrated circuit seldom has a predetermined duty ratio because of various factors, such as a noise, that arise once the semiconductor integrated circuit is mounted, e.g., on a Printer Circuit Board (PCB). Thus, a conventional semiconductor integrated circuit generally includes a duty cycle correcting circuit that corrects a duty ratio of the clocks to improve the operation efficiency.
Such a conventional duty cycle correcting circuit has been implemented in such a manner that the duty cycle correcting circuit includes a dual loop, and is configured to match rising edges of two clocks and mix the phases of the two clocks.
Generally, however, a conventional duty cycle correcting circuit has a complicated structure, and may produce errors when the rising edges of the two clocks at issue are mismatched to each other. Such mismatches are common in conventional semiconductor integrated circuits due to changes in the Process, Voltage, and Temperature (PVT) effecting or related to the device. For this reason, the operation efficiency of conventional duty cycle correcting circuit can be poor, and they can produce errors. Further, conventional duty cycle correcting circuit tend to occupy a large area and consume a significant amount of power. Further, it can be difficult to implement design changes to improve the performance or reduce the footprint of conventional duty cycle correcting circuits.